PRODUCT FEATURES  

Compliant with 100GBASE-LR4

Support line rates from 103.125 Gbps to 111.81 Gbps

Integrated LAN WDM TOSA / ROSA for up to 10 km reach over SMF

Digital Diagnostics Monitoring Interface

Duplex LC optical receptacle

No external reference clock

Single 3.3 V power supply

Case operating temperature range:0°C to 70°C  

Power dissipation < 6W

Application

Local Area Network (LAN)

Data Center

Ethernet switches and router applications

STANDARD

Compliant to IEEE 802.3ba

Compliant to CFP MSA CFP4 Hardware Specification

Compliant to CFP MSA Management Interface Specification

General Description

    100G CFP4 LR4 optical Transceiver integrates receiver and transmitter path on one module. In the transmit side, four lanes of serial data streams are recovered, retimed, and passed to four laser drivers. The laser drivers control four EMLs (Electric-absorption Modulated Lasers) with center wavelength of 1296 nm, 1300nm, 1305nm and 1309 nm. The optical signals are multiplexed to a single –mode fiber through an industry standard LC connector. In the receive side, the four lanes of optical data streams are optically de-multiplexed by the integrated optical de-multiplexer. Each data stream is recovered by a PIN photo-detector and trans-impedance amplifier, retimed. This module features a hot-pluggable electrical interface, low power consumption and MDIO management interface.

     The module provides an aggregated signaling rate from 103.125 Gbps to 111.81 Gbps. It is compliant with IEEE 802.3 ba 100GBASE-LR4 and ITU-T G.959.1, and OIF CEI-28G-VSR. The MDIO management interface complies with IEEE 802.3 Clause 45 standard. The transceiver complies with CFP MSA CFP4 Hardware Specification, CFP MSA Management Interface Specification, and OIF CEI-28G-VSR standards. A block diagram is shown in Figure 1. 

Figure 1. CFP4 LR4 Optical Transceiver functional block diagram

Transmitter

The transmitter path converts four lanes of serial NRZ electrical data from line rate of 25.78 Gbps to 27.95 Gbps to a standard compliant optical signal. Each signal path accepts a 100 Ω differential 100 mV peak-to-peak to 900 mV peak-to-peak 25 Gbps electrical signal on TDxn and TDxp pins. Inside the module, each differential pair of electric signals is input to a CDR (clock-data recovery) chip. The recovered and retimed signals are then passed to a laser driver which transforms the small swing voltage to an output modulation that drives a EML laser. The laser drivers control four EMLs with center wavelengths of 1295.56 nm, 1300.05 nm, 1304.58 nm and 1309.14 nm. The optical signals from the four lasers are multiplexed together optically. The combined optical signals are coupled to single-mode optical fiber through an industry standard LC optical connector.

Receiver

The receiver takes incoming combined four lanes optical data from line rate of 25.78 Gbps to 27.95 Gbps through an industry standard LC optical connector. The four incoming wavelengths are separated by an optical de-multiplexer into four separated channels. Each output is coupled to a PIN photo-detector. The electrical currents from each PIN photo-detector are converted to a voltage with a high-gain trans-impedance amplifier. The electrical output is recovered and retimed by the CDR chip. The four lanes of reshaped electrical signals are output to RDxp and RDxn pins.

Low Speed Signaling

Low speed signaling is based on low voltage CMOS (LVCMOS) operating at a nominal voltage of 3.3 V for the control and alarm signals, and at a nominal voltage of 1.2 V for MDIO address, clock and data signals. All low speed inputs and outputs are based on the CFP MSA CFP4 Hardware Specification and CFP MSA Management Interface Specification.

MDC/MDIO: Management interface clock and data lines.

PRTADR0, 1, 2: Input pins. MDIO physical port addresses.

GLB_ALEMn: Output pin. When asserted low indicates that the module has detected an alarm condition in any MDIO alarm register.

TX_Disable: Input pin. When asserted high or left open the transmitter output is turned off. When Tx_Dsiable is asserted low or grounded the module transmitter is operating normally. Pulled up with 4.7 kΩ to 10 kΩ resistors to 3.3 V inside the CFP4 module.

MOD_LOPWR: Input pin. When asserted high or left open the CFP4 module is in low power mode. When asserted low or grounded the module is operating normally. Pulled up with 4.7 kΩ to 10 kΩ resistors to 3.3 V inside the CFP4 module.

MOD_RSTn: Input pin. When asserted low or grounded the module is in Reset mode. When asserted high or left open the CFP4 module is operating normally after an initialization process. Pulled down with 4.7 kΩ to 10 kΩ resistors to ground inside the CFP4 module.

Mod_ABS: Output pin. Asserted high when the CFP4 module is absent and is pulled low when the CFP4 module is inserted.

RX_LOS: Output pin. Asserted high when insufficient optical power for reliable signal reception is received.

Pin Function Definitions

Figure 2  CFP4 optical transceiver pin-out

Table 1 CFP4 optical transceiver pin descriptions

      Absolute Maximum Ratings

      Low Speed Electrical Characteristics

      High Speed Electrical Specifications 

       MDIO Management Interface 

   The HC CFP4 Optical Transceiver incorporates MDIO management interface which is used for serial ID, digital diagnostics, and certain control and status report functions. The CFP4 transceiver supports MDIO pages 8000h NVR 1 Based ID registers, 8080h NVR 2 Extended ID registers, 8100h NVR 3 network lane specific registers , 8180h NVR 4 registers ,and pages A000h module VR 1 registers(module level control and DDM registers)， A200h network lane VR 1 registers，A280h network lane VR 2 registers,A400h host lane VR1 specific registers.

   Details of the protocol and interface are explicitly described in CFP MSA Management Interface Specification. Please refer to the specifications for design reference.

       Optical Transmitter Characteristics

        Optical Receiver Characteristics

Lower Memory Map

The lower 128 bytes of the 2-wire serial bus address space, see Table 1, is used to access a variety of

measurements and diagnostic functions, a set of control functions, and a means to select which of the various upper memory map pages are accessed on subsequent reads. This portion of the address space is always directly addressable and thus is chosen for monitoring and control functions that may need to be repeatedly accessed. The definition of identifier field is the same as page 00h Byte 128.

Table 1— Lower Memory Map

      Outline Dimensions:mm

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